1. Field of the Invention
The present invention relates generally to stereolithography and, more specifically, to a platen apparatus and method of using the platen apparatus to provide gross location, planarization, and mechanical restraint to electronic components and assemblies before, during, and after stereolithography processes.
2. State of the Art
In the past decade, a three-dimensional manufacturing technique termed “stereolithography,” also known as “layered manufacturing,” has evolved to a degree where it is employed in many industries.
Essentially, stereolithography, as conventionally practiced, involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or “sliced” into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries, followed by selective consolidation or fixation of the material to at least a semisolid state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer. The unconsolidated material employed to build an object may be supplied in particulate or liquid form, and the material itself may be consolidated, fixed or cured, or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size, whereas when a liquid is employed, resolution is highly dependent upon the minimum surface area of the liquid which can be fixed (cured) and the minimum thickness of a layer which can be generated given the viscosity of the liquid and other parameters such as transparency to radiation or particle bombardment used to effect at least a partial cure of the liquid to a structurally stable state. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed might be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design is committed to large-scale production.
Stereolithography has also been employed to develop and refine object designs in relatively inexpensive materials and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive for same, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques.
More recently, stereolithography has been used to apply material to preformed electronic components and resulting structures with a high degree of precision. For example, stereolithographic techniques may be used to apply protective or alignment structures to substrates. A substrate used for effecting electrical testing of semiconductor devices or to connect same to each other or to higher level packaging may be provided with a protective structure in the form of a layer of dielectric material having a controlled thickness or depth and defining precisely sized, shaped and located apertures through which conductive terminals on the surface of the substrate may be accessed for testing of a semiconductor die disposed on the substrate.
The dielectric layer, in addition to physically protecting, sealing and isolating circuit traces on the substrate from contact with connective elements on the superimposed semiconductor die to prevent shorting, may be employed as desired as a structure to mechanically align the semiconductor die with the substrate for proper communication of the connective elements with the substrate terminals. This may be effected in the context of a so-called “flip-chip” semiconductor die bearing a pattern of discrete connective elements projecting transversely from the active surface of the die (such as solder bumps or conductive or conductor-bearing polymers), by using precisely sized and located apertures in the dielectric material to partially receive the connective elements. In addition to, or in lieu of, such an alignment structure approach, upwardly projecting alignment elements comprising the same material as that of the dielectric layer may be fabricated on the dielectric layer. Such alignment elements may, for example, comprise C-shaped projections located on opposing sides of an intended location for the semiconductor die, L-shaped projections at corners of the intended die location, or linear segments parallel to, and defining a slightly larger area than, the side of a rectangular die.
Such protective or alignment elements may be applied to a dielectric layer or layer segments using stereolithographic techniques. Formation of the protective or alignment structures is accomplished by suspending a substrate on a support platform within a reservoir containing a curable liquid as commonly used in stereolithography (typically a photopolymer). The platform is vertically moveable such that a substrate suspended thereon may be moved in precise increments into or out of the curable liquid. Layer thickness and shape for the desired stereolithographic formations are typically programmed into a computer control system which monitors the stereolithographic process. In response to the control system, the platform upon which a substrate is suspended is lowered into the reservoir to a desired depth within the liquid such that a layer of curable liquid in the reservoir covers or lies adjacent a certain level with respect to the suspended substrate. Precisely focused electromagnetic radiation in the form of an ultraviolet (UV) wavelength laser is triggered to fix or cure at least a portion of the liquid material on or adjacent the substrate. The platform is then lowered by a distance equal to the thickness of the next desired layer to provide a new layer of curable liquid and the laser is again triggered to cure at least a portion of the liquid. The process is then repeated layer by layer until the desired stereolithographic structure is formed on and about the substrate. The platform is then raised above the level of the liquid and the substrate with associated stereolithographic structure is removed.
It is also known to fabricate packaging for semiconductor dice using stereolithographic techniques. A semiconductor die is placed on a platform of a stereolithography apparatus or on stereolithographically formed supports on the platform. As discussed above, the platform is lowered into the reservoir to a desired liquid depth such that a layer of the curable liquid covers or lies adjacent a certain level with respect to the suspended semiconductor die. Precisely focused electromagnetic radiation in the form of an ultraviolet (UV) wavelength laser is triggered to fix or cure at least a portion of the liquid material in a desired pattern on or adjacent the semiconductor die. The platform is then lowered by a distance equal to the thickness of the next desired layer to provide a new layer of curable liquid and the laser is again triggered to cure at least a portion of the liquid in a desired pattern. The process is then repeated layer by layer until the desired stereolithographic structure is formed on and about the semiconductor die. The process may be used to define a dielectric layer about bond pad or conductive bump locations, over wire bonds, over portions of leads, or as otherwise desired. The platform is then raised above the level of the liquid and the semiconductor die with associated stereolithographic structure is removed.
By their diminutive nature in terms of gross dimensions and the minute features and elements thereof, semiconductor dice and other components such as test interposers, leads and other connective elements, interposers for converting dice to a flip-chip configuration and other, similar structures (hereinafter generally and collectively termed “electronic components”) are very fragile and susceptible to damage in addition to lacking structural rigidity, including torsional rigidity. This is particularly true of bare (unpackaged) semiconductor dice. Thus, exposure of semiconductor dice and other minute components to the processing and handling steps involved in stereolithographic methods can result in damage to or destruction of the components.
In addition, while it may be possible to form stereolithographic structures on one or more electronic components secured to, for example, circuit boards, interposers and lead frame strips (hereinafter generally and collectively referred to as “carrier substrates”), such combinations of electronic components and carrier substrates being termed “electronic component assemblies” herein, location of such component-bearing elements is perceived to present a problem. In addition, any lack of planarity of such carrier substrates, which may be accentuated by warping and twisting during processing as well as handling between process steps, may compromise planarity of an electronic component about or on which stereolithographic structures are formed, resulting (by way of example only) in uneven coverage of one or more surfaces, elements or features of a semiconductor die being packaged or, in the instance of an alignment or support structure being formed, unsatisfactory dimensional tolerances which may lead to misalignment with respect to another component such as a die, interposer or other substrate to be subsequently associated with the alignment or support structure being fabricated.
Further, damage may occur to the electronic components or the electronic component assemblies during the transferring of the electronic component to the platform of the stereolithography apparatus, during removal of the electronic component from the platform, and during the stereolithographic process itself.
Moreover, the inventor herein has recognized that fabricating stereolithographic structures in association with a large plurality of electronic components or electronic component assemblies, such as would be required to implement at least partially automated stereolithographic techniques in the electronics industry on a commercial basis, will require assurance of at least gross positioning and planarity of all electronic components and/or assemblies carrying such electronic components on a given stereolithography platform and, desirably, a technique to mechanically restrain such components to their locations during different processing and handling steps before, during and after stereolithography. The aforementioned reasons as to the need for planarity should be readily apparent from the description above but, as to the need for gross positioning, a further explanation may be in order.
It has been disclosed and claimed in U.S. patent application Ser. No. 09/259,142, assigned to the assignee of the present invention and issued as U.S. Pat. No. 6,549,821, to modify a conventional stereolithography apparatus such as those offered by 3D Systems, Inc. with a machine vision system to precisely locate features on electronic components so as to enable fabrication of stereolithographic structures thereon. While a machine vision system enables fabrication of such structures on a large plurality of electronic components residing on a platform of a stereolithography apparatus and while a machine vision system may be employed to plot the gross (general) location and orientation of electronic components on a platform, such an approach may undesirably consume computer processing power as well as require a machine vision system employing two camera systems, one for determining the gross locations and orientations of the electronic components and another one for focusing on the surfaces, elements and features of an individual electronic component for precise placement of stereolithographic structures thereon. In addition, such an approach still requires handling of individual electronic components or electronic component assemblies to place same on the platform for fabrication of the stereolithographic structures and remove same after fabrication thereof for further processing. This necessity both enhances the potential for damage and contamination and inhibits automation of the stereolithography process for the described applications.
Thus, it would be desirable to provide an apparatus and method for gross location and orientation of, restraint of and assuring planarity of pluralities of electronic components and electronic component assemblies undergoing stereolithography processes and to facilitate handling of the pluralities of electronic components and electronic component assemblies.